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1 typical application features description dual, 16-bit, 5msps differential input adc with wide input common mode range the ltc ? 2323- 16 is a low noise, high speed dual 16- bit successive approximation register (sar) adc with differential inputs and wide input common mode range. operating from a single 3.3v or 5v supply, the lt c2323 -16 has an 8v p-p differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. the lt c2323 -16 achieves 4lsb inl typical, no missing codes at 16 bits and 81db snr. the ltc2323 -16 has an onboard low drift (20ppm / c max) 2.048v or 4.096v temperature-compensated reference. the ltc2323 -16 also has a high speed spi-compatible serial interface that supports cmos or lvds. the fast 5msps per channel throughput with one-cycle latency makes the ltc2323-16 ideally suited for a wide variety of high speed applications. the ltc2323 -16 dissipates only 40mw per channel and offers nap and sleep modes to reduce the power consumption to 5w for further power savings during inactive periods. 32k point fft f s = 5msps, f in = 2.2mhz applications n 5msps throughput rate n 4lsb inl (typ) n guaranteed 16-bit, no missing codes n 8v p-p differential inputs with wide input common mode range n 81db snr (typ) at f in = 2mhz n C85db thd (typ) at f in = 2mhz n guaranteed operation to 125c n single 3.3v or 5v supply n low drift (20ppm/c max) 2.048v or 4.096v internal reference n 1.8 v to 2.5v i/o voltages n cmos or lvds spi-compatible serial i/o n power dissipation 40mw/ch ( typ ) n small 28-lead (4mm 5mm) qfn package n high speed data acquisition systems n communications n remote data acquisition n imaging n optical networking n automotive n multiphase motor control l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. bipolar 25 25 220pf unipolar arbitrary differential inputs no configuration required in + , in ? differential ov dd v dd ltc2323-16 v dd ognd gnd 1.8v to 2.5v 232316 ta01a 10f 3.3v or 5v sdo1 0v 0v 0v 0v refout2 vbyp1 refout1 vbyp2 sdo2 clkout a in1 ? a in2 ? a in2 + a in1 + sck cnv refint cmos /lvds 1f to control logic (fpga, cpld, dsp, etc.) 1f 1f 10f 10f 232316 ta01b frequency (mhz) amplitude (dbfs) 0 2.5 2 1 0.5 1.5 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 snr = 81.4db thd = ?86.8db sinad = 80.3db sfdr = 88.2db lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
2 pin configuration absolute maximum ratings supply voltage (v dd ) .................................................. 6v su pply voltage (ov dd ) ................................................ 3v su pply bypass voltage (v by p1 , v by p2 ) ....................... 3v an alog input voltage a in + , a in C (note 3) ................... C 0. 3v to (v dd + 0.3v ) r efout1,2 ............................. . C 0.3v to (v dd + 0.3v ) cnv ( note 15) .......................... C 0. 3v to (v dd + 0.3v ) digital input voltage (note 3) .......................... (g nd C 0.3v ) to (ov dd + 0.3v ) digital output voltage (note 3) .......................... (g nd C 0.3v ) to (ov dd + 0.3v ) power dissipation ............................................... 2 00mw operating temperature range lt c23 23c ................................................ 0 c to 70 c lt c23 23 i ............................................. C 40 c to 85 c lt c23 23 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 29 gnd 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 v dd a in2 + a in2 ? gnd gnd a in1 ? a in1 + v dd sck ? sck + sdo2 ? sdo2 + clkout ? clkout + sdo1 ? sdo1 + refint refrtn2 refout2 cmos/lvds vbyp2 ognd cnv gnd refrtn1 refout1 vbyp1 ov dd 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 43c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2323cufd-16#pbf ltc2323cufd-16#trpbf 23236 28-lead (4mm 5mm) plastic qfn 0c to 70c ltc2323iufd-16#pbf ltc2323iufd-16#trpbf 23236 28-lead (4mm 5mm) plastic qfn C40c to 85c ltc2323hufd-16#pbf ltc2323hufd-16#trpbf 23236 28-lead (4mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (a in1 + , a in2 + ) (note 5) l 0 v dd v v in C absolute input range (a in1 C , a in2 C ) (note 5) l 0 v dd v v in + C v in C input differential voltage range v in = v in + C v in C l Crefout1,2 refout1,2 v v cm common mode input range v in = (v in + + v in C )/2 l 0 v dd v i in analog input dc leakage current l C1 1 a c in analog input capacitance 10 pf cmrr input common mode rejection ratio f in = 2.2mhz 85 db i refout external reference current refint = 0v, refout = 4.096v 675 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). http://www.linear.com/product/ltc2323-16#orderinfo lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
3 dynamic accuracy converter characteristics symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise 1.5 lsb rms inl integral linearity error (note 6) l C12 4 12 lsb dnl differential linearity error l C0.99 0.4 0.99 lsb bze bipolar zero-scale error (note 7) l C12 0 12 lsb bipolar zero-scale error drift 0.01 lsb/c fse bipolar full-scale error v refout1,2 = 4.096v (refint grounded) (note 7) l C90 10 90 lsb bipolar full-scale error drift v refout1,2 = 4.096v (refint grounded) 15 ppm/c symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 2.2mhz, v refout1,2 = 4.096v, internal reference l 76 80 db f in = 2.2mhz, v refout1,2 = 5v, external reference 80 db snr signal-to-noise ratio f in = 2.2mhz, v refout1,2 = 4.096v, internal reference l 76.5 81 db f in = 2.2mhz, v refout1,2 = 5v, external reference 81.7 db thd total harmonic distortion f in = 2.2mhz, v refout1,2 = 4.096v, internal reference l C87 C80 db f in = 2.2mhz, v refout1,2 = 5v, external reference C88 db sfdr spurious free dynamic range f in = 2.2mhz, v refout1,2 = 4.096v, internal reference l 78 91 db f in = 2.2mhz, v refout1,2 = 5v, external reference 88 db C3db input linear bandwidth 10 mhz aperture delay 500 ps aperture delay matching 500 ps aperture jitter 1 ps rms transient response full-scale step 3 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs (notes 4, 8). internal reference characteristics symbol parameter conditions min typ max units v refout1,2 internal reference output voltage 4.75v < v dd < 5.25v 3.13v < v dd < 3.47v l l 4.088 2.044 4.096 2.048 4.106 2.053 v v refin temperature coefficient (note 14) l 3 20 ppm/c refout1,2 output impedance 0.25 v refout1,2 line regulation v dd = 4.75v to 5.25v 0.3 mv/v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
4 digital inputs and digital outputs power requirements symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = -500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma v id lvds differential input voltage 100 differential termination, ov dd = 2.5v l 240 600 mv v is lvds common mode input voltage 100 differential termination, ov dd = 2.5v l 1 1.45 v v od lvds differential output voltage 100 differential load, lvds mode, ov dd = 2.5v l 100 150 300 mv v os lvds common mode output voltage 100 differential load, lvds mode, ov dd = 2.5v l 0.85 1.2 1.4 v v od_lp low power lvds differential output voltage 100 differential load, low power, lvds mode ,ov dd = 2.5v l 75 100 250 mv v os_lp low power lvds common mode output voltage 100 differential load, low power, lvds mode ,ov dd = 2.5v l 0.9 1.2 1.4 v symbol parameter conditions min typ max units v dd supply voltage 5v operation 3.3v operation l l 4.75 3.13 5.25 3.47 v v ov dd supply voltage l 1.71 2.63 v i vdd supply current 5msps sample rate (in + = in C = 0v) l 14.5 18 ma i ovdd supply current 5msps sample rate (c l = 5pf) cmos mode 5msps sample rate (r l = 100) lvds mode l l 4 8 5 12 ma ma i nap nap mode current conversion done (i vdd ) l 3 5 ma i sleep sleep mode current sleep mode (i vdd + i ovdd ) cmos mode sleep mode (i vdd + i ovdd ) lvds mode l l 1 1 5 5 a a p d_3.3v power dissipation v dd = 3.3v 5msps sample rate (in + = in C = 0v) cmos mode v dd = 3.3v 5msps sample rate (in + = in C = 0v) lvds mode l l 55 65 58 86 mw mw nap mode v dd = 3.3v conversion done (i vdd + i ovdd ) cmos mode v dd = 3.3v conversion done (i vdd + i ovdd ) lvds mode l l 10 31 13 41 mw mw sleep mode v dd = 3.3v sleep mode (i vdd + i ovdd ) cmos mode v dd = 3.3v sleep mode (i vdd + i ovdd ) lvds mode l l 5 5 16.5 16.5 w w p d_5v power dissipation v dd = 5v 5msps sample rate (in + = in C = 0v) cmos mode v dd = 5v 5msps sample rate (in + = in C = 0v) lvds mode l l 80 95 100 110 mw mw nap mode v dd = 5v conversion done (i vdd + i ovdd ) cmos mode v dd = 5v conversion done (i vdd + i ovdd ) lvds mode l l 15 31 25 40 mw mw sleep mode v dd = 5v sleep mode (i vdd + i ovdd ) cmos mode v dd = 5v sleep mode (i vdd + i ovdd ) lvds mode l l 5 5 25 25 w w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
5 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground, or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground, or above v dd or ov dd , without latch-up. note 4: v dd = 5v, ov dd = 2.5v, refout1,2 = 4.096v, f smpl = 5mhz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs un-trimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 4.096v input with refin = 4.096v. note 9: when refout1,2 is overdriven, the internal reference buffer must be turned off by setting refint = 0v. note 10: f smpl = 5mhz, i refbuf varies proportionally with sample rate. note 11: guaranteed by design, not subject to test. note 12: parameter tested and guaranteed at ov dd = 1.71v and ov dd = 2.5v. note 13: t sck of 9.4ns maximum allows a shift clock frequency up to 105mhz for rising edge capture. note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 15: cnv is driven from a low jitter digital source, typically at ov dd logic levels. this input pin has a ttl style input that will draw a small amount of current. figure?1. voltage levels for timing specifications 0.8 ? ov dd 0.2 ? ov dd 50% 50% 232316 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay adc timing characteristics symbol parameter conditions min typ max units f smpl maximum sampling frequency l 5 msps t cyc time between conversions (note 11) l 200 1000000 ns t acq acquisition time (note 11) l 28.5 ns t conv conversion time l 171.5 ns t cnvh cnv high time l 25 ns t dcnvsckl sck quiet time from cnv (note 11) l 9.5 ns t dscklcnvh sck delay time from cnv (note 11) l 19.1 ns t sck sck period (notes 12, 13) l 9.4 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns t dsckclkout sck to clkout delay (note 12) l 3 ns t dclkoutsdov sdo data valid delay from clkout c l = 5pf (note 12) l 2 ns t hsdo sdo data remains valid delay from clkout c l = 5pf (note 11) l 2 ns t dcnvsdov sdo data valid delay from cnv c l = 5pf (note 11) l 2.5 3 ns t dcnvsdoz bus relinquish time after cnv (note 11) l 3 ns t wake refout1,2 wakeup time c refout1,2 = 10f 10 ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
6 typical performance characteristics thd, harmonics vs input common mode (100khz to 2.2mhz) snr, sinad vs reference voltage, f in = 500khz 8k point fft, imd, f s = 5msps, a in + = 100khz, a in C = 2.2mhz 32k point fft, f s = 5msps, f in = 2.2mhz snr, sinad vs input frequency (100khz to 2.2mhz) thd, harmonics vs input frequency (100khz to 2.2mhz) integral nonlinearity vs output code differential nonlinearity vs output code dc histogram t a = 25c, v dd = 5v, ov dd = 2.5v, refout1,2 = 4.096v, f smpl = 5msps, unless otherwise noted. output code 0 ?8 ?4 ?6 inl error (lsb) ?2 2 0 4 6 8 16384 32768 ?32768 ?16384 232316 g01 output code 0 ?1.0 dnl error (lsb) 0 ?0.5 0.5 1.0 16384 32768 ?32768 ?16384 232316 g02 code counts 8000 18000 20000 ?4 ?2 0 4000 14000 6000 16000 2000 0 12000 10000 ?5 ?3 2 6 ?1 1 4 53 232316 g03 j = 1.5 232316 g04 frequency (mhz) amplitude (dbfs) 0 2.5 2 1 0.5 1.5 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 snr = 81.4db thd = ?86.8db sinad = 80.3db sfdr = 88.2db frequency (mhz) 0 80.0 80.5 snr, sinad level (dbfs) 81.5 81.0 82.0 82.5 83.0 1 0.5 1.5 2 2.5 232316 g05 sinad snr frequency (mhz) ?110 ?105 thd, harmonics level (dbfs) ?100 ?95 ?90 ?85 232316 g06 0 1 0.5 1.5 2 2.5 hd2 hd3 thd input common mode (v) 1.7 thd, harmonics level (dbfs) ?90 ?85 ?80 3.1 ?95 ?100 2.1 2.5 1.9 2.3 2.7 2.9 3.3 ?105 ?110 ?75 232316 g07 hd2 hd3 thd v ref (v) 0.5 snr, sinad (dbfs) 78 80 4 76 74 1.5 2.5 1 2 3 4.5 3.5 5 68 72 82 70 232316 g08 sinad snr 232316 g09 frequency (mhz) amplitude (dbfs) 0 2.5 2 1 0.5 1.5 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
7 typical performance characteristics offset error vs temperature gain error vs temperature refout1,2 output vs temperature i ref vs temperature, v ref = 4.096v supply current vs sample frequency ov dd current vs sck frequency, c load = 10pf crosstalk vs input frequency cmrr vs input frequency output match with simultaneous input steps at ch1, ch2 t a = 25c, v dd = 5v, ov dd = 2.5v, refout1,2 = 4.096v, f smpl = 5msps, unless otherwise noted. frequency (mhz) ?104 ?95 ?98 ?101 cmrr (db) ?92 ?89 ?83 ?86 ?80 232316 g11 0 1 0.5 1.5 2 2.5 frequency (mhz) ?136 ?134 crosstalk (dbc) ?132 ?130 ?128 ?126 232316 g10 0 1 0.5 1.5 2 2.5 232316 g12 time (ns) output code (ch1, ch2) 0 200 100 35000 30000 25000 20000 15000 10000 5000 0 ?5000 ch2 ch1 temperature (c) ?50 lsb 0.50 1.00 1.50 125 0 ?0.50 0 50 ?25 25 75 100 150 ?2.00 ?2.50 ?1.00 2.00 ?1.50 232316 g13 ch1 ch2 temperature (c) ?40 gain error (16-bit lsb) 0.5 1.0 0 ?0.5 0 50 ?25 25 75 100 125 ?1.0 ?1.5 1.5 232316 g14 232316 g15 temperature (c) refout (ppm) ?50 150 50 0 100 200 100 0 ?100 ?200 ?300 ?400 ?500 2.048v 4.096v temperature (c) ?40 reference current (ma) 0.675 100 0 40 ?20 20 60 80 120 0.665 0.670 0.680 232316 g16 sample frequency (msps) 8 10 supply current (ma) 12 14 16 232316 g17 0 21 3 4 5 6 sck frequency (mhz) 0 2 ov dd current (ma) 4 6 8 232316 g18 0 20 40 60 10 30 80 50 70 100 11090 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
8 pin functions v dd (pins 1, 8): power supply. bypass v dd to gnd with a 10f ceramic and a 0.1f ceramic close to the part. the v dd pins should be shorted together and driven from the same supply. a in2 + , a in2 C (pins 2, 3): analog differential input pins. full-scale range (a i n2 + C a i n2 C ) is refout2 voltage. these pins can be driven from v dd to gnd. gnd (pins 4, 5, 10, 29): ground. these pins and exposed pad (pin 29) must be tied directly to a solid ground plane. a in1 C , a in1 + (pins 6, 7): analog differential input pins. full-scale range (a i n1 + C a i n1 C ) is refout1 voltage. these pins can be driven from v dd to gnd. cnv (pin 9): conversion start input. a falling edge on cnv puts the internal sample-and-hold into the hold mode and starts a conversion cycle. cnv must be driven by a low jitter clock as shown in the application circuit on page?26. the cnv pin is unaffected by the cmos /lvds pin. refrtn1 (pin 11): reference buffer 1 output return. bypass refrt n1 to refout1. do not tie the refrtn1 pin to the ground plane. refout1 (pin 12) : reference buffer 1 output. an onboard buffer nominally outputs 4.096v to this pin. this pin is referred to refrt n1 and should be decoupled closely to the pin (no vias) with a 0.1f (x7r, 0402 size) capacitor and a 10f (x5r, 0805 size) ceramic capacitor in paral - lel. the internal buffer driving this pin may be disabled by grounding the refint pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to 5v. vbyp1 (pin 13): bypass this internally supplied pin to ground with a 1f ceramic capacitor. the nominal output voltage on this pin is 1.6v. ov dd (pin 14): i/o interface digital power. the range of ov dd is 1.71v to 2.5v . this supply is nominally set to the same supply as the host interface (cmos : 1.8v or 2.5v , lvds : 2.5v). bypass ov dd to ognd with a 0.1f capacitor. sdo1 + , sdo1 C (pins 15, 16): channel 1 serial data output. the conversion result is shifted msb first on each falling edge of sck. in cmos mode, the result is output on sdo1 + . the logic level is determined by ov dd . do not connect sdo1 C . in lvds mode, the result is output differentially on sdo1 + and sdo1 C . these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). clkout + , clkout C (pins 17, 18) : serial data clock output. clkout provides a skew-matched clock to latch the sdo output at the receiver. in cmos mode, the skew- matched clock is output on clkout + . the logic level is determined by ov dd . do not connect clkout C . for low throughput applications using sck to latch the sdo out - put, clkout + can be disabled by tying clkout C to ov dd . in lvds mode, the skew-matched clock is output differ - entially on clkout + and clkout C . these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). sdo2 + , sdo2 C (pins 19, 20): channel 2 serial data output. the conversion result is shifted msb first on each falling edge of sck. in cmos mode, the result is output on sdo2 + . the logic level is determined by ov dd . do not connect sdo2 C . in lvds mode, the result is output differentially on sdo2 + and sdo2 C . these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). sck + , sck C (pins 21, 22): serial data clock input. the falling edge of this clock shifts the conversion result msb first onto the sdo pins. in cmos mode, drive sck + with a single-ended clock. the logic level is determined by ov dd . do not connect sck C . in lvds mode, drive sck + and sck C with a differential clock. these pins must be differentially terminated by an external 100 resistor at the receiver (adc). ognd (pin 23): i/o ground. this ground must be tied to the ground plane at a single point. ov dd is bypassed to this pin. lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
9 pin functions vbyp2 (pin 24): bypass this internally supplied pin to ground with a 1f ceramic capacitor. the nominal output voltage on this pin is 1.6v cmos /lvds (pin 25): i/o mode select. ground this pin to enable cmos mode, tie to ov dd to enable lvds mode. float this pin to enable low power lvds mode. refout2 (pin 26) : reference buffer 2 output. an onboard buffer nominally outputs 4.096v to this pin. this pin is referred to refrt n2 and should be decoupled closely to the pin (no vias) with a 0.1f (x7r, 0402 size) capacitor and a 10f (x5r, 0805 size) ceramic capacitor in paral - lel. the internal buffer driving this pin may be disabled by grounding the refint pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to v dd . refrtn2 (pin 27) : reference buffer 2 output return. bypass refrt n2 to refout2. do not tie the refrtn2 pin to the ground plane. refint (pin 28): reference buffer output enable. tie to v dd when using the internal reference. tie to ground to disable the internal refout1 and refout2 buffers for use with external voltage references. this pin has a 500k internal pull-up to v dd . exposed pad (pin 29) : ground. solder this pad to ground. lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
10 functional block diagram timing diagram b15 b14 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b13 cnv sck clkout sdo acquisition conversion and readout serial data bits b[15:0] correspond to previous conversion acquisition hi-z hi-z 232316 td 15 13 16 16-bit sar adc lvds/cmos tri-state serial output output clock driver lvds/cmos receivers sdo1 + sd01 ? 14 gnd 4, 5, 10, 29 ov dd 7 6 a in1 + 12 refout1 28 refint 26 refout2 a in1 ? 17 18 clkout + clkout ? 21 22 sck + sck ? timing control logic 232316 bd ? + s/h ldo ldo 19 20 16-bit sar adc lvds/cmos tri-state serial output sdo2 + sdo2 ? 24 vbyp2 2 3 a in2 + 9 cnv a in2 ? v dd 1,8 v dd 1,8 vbyp1 ? + s/h g g 1.2v ref lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
11 applications information overview the ltc2323 -16 is a low noise, high speed 16-bit succes - sive approximation register (sar) adc with differential inputs and a wide input common mode range. operating from a single 3.3v or 5v supply, the ltc2323-16 has an 8v p-p differential input range, making it ideal for applica - tions which require a wide dynamic range. the ltc2323- 16 achieves 4lsb inl typical, no missing codes at 16 bits and 81db snr. the ltc2323 -16 has an onboard reference buffer and low drift (20ppm/c max) 4.096v temperature-compensated reference. the ltc2323-16 also has a high speed spi- compatible serial interface that supports cmos or lvds. the fast 5msps per channel throughput with one-cycle latency makes the ltc2323-16 ideally suited for a wide variety of high speed applications. the ltc2323-16 dis- sipates only 45mw per channel. nap and sleep modes are also provided to reduce the power consumption of the ltc2323 -16 during inactive periods for further power savings. converter operation the ltc2323 -16 operates in two phases. during the acquisition phase, the sample capacitor is connected to the analog input pins a in + and a in C to sample the dif - ferential analog input voltage, as shown in figure?3. a falling edge on the cnv pin initiates a conversion. during the conversion phase, the 16- bit cdac is sequenced through a successive approximation algorithm for each input sck pulse, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g., v refout /2, v refout /4 v refout /32768) using a differential comparator. at the end of conversion, a cdac output approximates the sampled analog input. the adc control logic then prepares the 16-bit digital output code for serial transfer. transfer function the ltc2323 -16 digitizes the full-scale voltage of 2 refout1,2 into 2 16 levels, resulting in an lsb size of 125v with refbuf = 4.096v. the ideal transfer function is shown in figure?2. the output data is in 2 s comple - ment format. analog input the differential inputs of the ltc2323 -16 provide great flexi bility to convert a wide variety of analog signals with no configuration required. the ltc2323 -16 digitizes the difference voltage between the a in + and a in C pins while supporting a wide common mode input range. the analog input signals can have an arbitrary relationship to each other, provided that they remain between v dd and gnd. the ltc2323 -16 can also digitize more limited classes of analog input signals such as pseudo-differential unipolar/ bipolar and fully differential with no configuration required. the analog inputs of the ltc2323 -16 can be modeled by the equivalent circuit shown in figure?3. the back-to- back diodes at the inputs form clamps that provide esd figure?2. ltc2323-16 transfer function figure?3. the equivalent circuit for the differential analog input of the ltc2323-16 r on 15 r on 15 bias voltage 232316 f03 c in 10pf v dd c in 10pf v dd a in1 ? a in1 + input voltage (v) ?fsr/2 +fsr/2 ? 1lsb output code (two?s complement) 232316 f02 011...111 011...110 111...111 100...000 100...001 000...000 000...001 ?1 lsb fsr = +fs ? ?fs 1lsb = fsr/65535 0 1 lsb lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
12 applications information protection. in the acquisition phase, 10pf (c in ) from the sampling capacitor in series with approximately 15 (r on ) from the on-resistance of the sampling switch is connected to the input. any unwanted signal that is com - mon to both inputs will be reduced by the common mode rejection of the adc sampler. the inputs of the adc core draw a small current spike while charging the c in capaci - tors during acquisition. single-ended signals single-ended signals can be directly digitized by the ltc2323-16. these signals should be sensed pseudo- differentially for improved common mode rejection. by connecting the reference signal (e.g., ground sense) of the main analog signal to the other a in pin, any noise or disturbance common to the two signals will be rejected by the high cmrr of the adc. the ltc2323-16 flexibil - ity handles both pseudo-differential unipolar and bipolar signals, with no configuration required. the wide common mode input range relaxes the accuracy requirements of any signal conditioning circuits prior to the analog inputs. pseudo-differential bipolar input range the pseudo-differential bipolar configuration represents driving one of the analog inputs at a fixed voltage, typi - cally v ref /2, and applying a signal to the other a in pin. in this case the analog input swings symmetrically around the fixed input yielding bipolar two s complement output codes with an adc span of half of full-scale. this con - figuration is illustrated in figure?4, and the corresponding transfer function in figure?5. the fixed analog input pin need not be set at v ref /2, but at some point within the v dd rails allowing the alternate input to swing symmetrically around this voltage. if the input signal (a in + ?C ?a in C ) swings beyond refout1,2/2, valid codes will be generated by the adc and must be clamped by the user, if necessary. figure?4. pseudo-differential bipolar application circuit figure?5. pseudo-differential bipolar transfer function 25 25 220pf v ref 0v v ref 0v v ref /2 v ref /2 v ref 10k 10k only channel 1 shown for clarity + ? + ? ltc2323-16 lt1819 232316 f04 sd01 vbyp1 refout1 clkout a in1 ? a in1 + sck to control logic (fpga, cpld, dsp, etc.) 1f 10f 1f 232316 f05 ?v ref ?16385 16384 ?32768 32767 v ref dotted regions available but unused a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
13 applications information pseudo-differential unipolar input range the pseudo-differential unipolar configuration represents driving one of the analog inputs at ground and applying a signal to the other a in pin. in this case, the analog input swings between ground and v ref yielding unipolar twos complement output codes with an adc span of half of full- scale. this configuration is illustrated in figure?6, and the corresponding transfer function in figure?7. if the input signal (a in + C a in C ) swings negative, valid codes will be generated by the adc and must be clamped by the user, if necessary. figure?6. pseudo-differential unipolar application circuit figure?7. pseudo-differential unipolar transfer function 232316 f07 ?v ref ?16385 16384 ?32768 32767 v ref dotted regions available but unused a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 25 25 220pf v ref 0v v ref 0v + ? ltc2323-16 lt1818 232316 f06 sdo1 vbyp1 refout1 clkout a in1 ? a in1 + sck to control logic (fpga, cpld, dsp, etc.) 1f 10f lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
14 applications information single-ended-to-differential conversion while single-ended signals can be directly digitized as previously discussed, single-ended to differential conver - sion circuits may also be used when higher dynamic range is desired. by producing a differential signal at the inputs of the ltc2323 -16, the signal swing presented to the adc is maximized, thus increasing the achievable snr. the lt ? 1819 high speed dual operational amplifier is recommended for performing single-ended-to-differen - tial conversions, as shown in figure?8. in this case, the first amplifier is configured as a unity-gain buffer and the single-ended input signal directly drives the high imped - ance input of this amplifier. fully-differential inputs to achieve the full distortion performance of the ltc2323-16, a low distortion fully-differential signal source driven through the lt1819 configured as two unity-gain buffers, as shown in figure?9, can be used. this circuit achieves the full data sheet thd specification of C85db at input frequencies of 500khz and less. data sheet typical perfor - mance curves taken at higher frequencies used a harmonic rejection filter between the adc and the signal source to eliminate the op amp as the dominant source of distortion. the fully-differential configuration yields an analog input span (a in + C a in C ) of refout1,2. in this configuration, the input signal is driven on each ain pin, typically at equal spans but opposite polarity. this yields a high com - mon mode rejection on the input signals. the common mode voltage of the analog input can be anywhere within the v dd input range, but will be limited by the peak swing of the full-range input signal. for example, if the internal reference is used with v dd = 5v dc , the full-range input span will be 4.096v . half of the input span is typically driven on each ain pin, yielding a signal span for each ain pin of 4.096v p-p . this leaves ~0.9v of common mode variation tolerance. when using external references, it is possible to increase common mode tolerance by com- pressing the adc full-range codes into a tighter range. for example, using an external 2.048v reference with v dd = 5v the total span would be 2.048v and each ain span would be limited to 2.048v p-p allowing a common mode range of ~3v . compressing the input span would incur a snr penalty of approximately 2db. input span compres - sion may be useful if single-supply analog input drivers figure?8. single-ended to differential driver figure?9. lt1819 buffering a fully-differential signal source v ref 0v v ref 0v v ref 0v v ref /2 + ? + ? 200 200 lt1819 232316 f08 v ref 0v v ref 0v v ref 0v v ref 0v + ? + ? lt1819 232316 f09 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
15 applications information are used which cannot swing rail-to-rail. the fully-differ - ential configuration is illustrated in figure?10, with the corresponding transfer function illustrated in figure?11. input drive circuits a low impedance source can directly drive the high imped - ance inputs of the ltc2323 -16 without gain error. a high impedance source should be buffered to minimize set - tling time during acquisition and to optimize the distor - tion performance of the adc. minimizing settling time is important even for dc inputs, because the adc inputs draw a current spike when during acquisition. for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2323-16. the amplifier provides low output impedance to minimize gain error and allow for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs, which draw a small current spike during acquisition. 25 25 220pf v ref 0v v ref 0v v ref 0v v ref 0v only channel 1 shown for clarity + ? + ? ltc2323-16 lt1819 232316 f10 sdo1 vbyp1 refout1 clkout a in1 ? a in1 + sck to control logic (fpga, cpld, dsp, etc.) 1f 10f 232316 f11 ?v ref ?16385 16384 ?32768 32767 v ref a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 figure?10. fully-differential application circuit figure?11. fully-differential transfer function lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
16 applications information input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. the simple 1-pole rc lowpass fil - ter shown in figure?12 is sufficient for many applications. the input resistor divider network, sampling switch on- resistance (r on ) and the sample capacitor (c in ) form a second lowpass filter that limits the input bandwidth to the adc core to 110mhz. a buffer amplifier with a low noise density must be selected to minimize the degrada - tion of the snr over this bandwidth. high quality capacitors and resistors should be used in the rc filters since these components can add distor - tion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. adc reference internal reference the ltc2323 -16 has an on-chip, low noise, low drift ( 20ppm / c max), temperature compensated bandgap reference. it is internally buffered and is available at refout1,2 (pins 12, 26). the reference buffer gains the internal reference voltage to 4.096v for supply volt - ages v dd = 5v and to 2.048v for v dd = 3.3v . bypass refout1,2 to refrt n1 ,2 with the parallel combination of a 0.1f (x7r, 0402 size) capacitor and a 10f (x5r, 0805 size) ceramic capacitor to compensate the reference buffer and minimize noise. the 0.1f capacitor should be as close as possible to the ltc2323 -16 package to minimize wiring inductance. tie the refint pin to v dd to enable the internal reference buffer. table 1. refout1,2 sources and ranges vs v dd v dd refint pin refout1,2 pin differential span 5v 5v internal 4.096v 4.096v 5v 0v external (1.25v to 5v) 1.25v to 5v 3.3v 3.3v internal 2.048v 2.048v 3.3v 0v external (1.25v to 3.3v) 1.25v to 3.3v 50 single-ended input signal 232316 f12 bw = 1mhz 3.3nf single-ended to differential driver in + in ? ltc2323 figure?12. input signal chain lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
17 applications information external reference the internal reference buffer can also be overdriven from 1.25v to 5v with an external reference at refout1,2 as shown in figure?13 (b and c). to do so, refint must be grounded to disable the reference buffer. a 55k inter - nal resistance loads the refout1,2 pins when the ref - erence buffer is disabled. to maximize the input signal swing and corresponding snr, the ltc6655 -5 is rec - ommended when overdriving refout. the ltc6655 -5 offers the same small size, accuracy, drift and extended temperature range as the ltc6655-4.096. by using a 5v reference, a higher snr can be achieved. we recommend bypassing the ltc6655-5 with a parallel combination of a 0.1f (x7r, 0402 size) ceramic capacitor and a 10f ceramic capacitor (x5r, 0805 size) close to each of the refout1,2 and refrtn1,2 pins. internal reference buffer transient response the refout1,2 pins of the ltc2323 -16 draw charge (q conv ) from the external bypass capacitors during each conversion cycle. if the internal reference buffer is over - driven, the external reference must provide all of this charge with a dc current equivalent to i ref = q conv /t cyc . thus, the dc current draw of refout1,2 depends on the sampling rate and output code. in applications where a burst of samples is taken after idling for long v dd ltc2323-16 gnd 232316 f13a 3.3v to 5v refout2 refout1 refrtn1 refrtn2 refint 0.1f 10f 0.1f 10f v in shdn v out_f v out_s ltc6655-4.096 ltc2323-16 gnd 232316 f13b 5v to 13.2v refout2 refout1 refrtn1 refrtn2 refint 0.1f 0.1f 10f 0.1f 10f v in shdn v out_f v out_s ltc6655-4.096 v in shdn v out_f v out_s ltc6655-2.048 ltc2323-16 gnd 232316 f13c 5v to 13.2v refout2 refout1 refrtn1 refrtn2 refint 0.1f 0.1f 0.1f 10f 0.1f 10f (13a) ltc2323-16 internal reference circuit (13b) ltc2323-16 with a shared external reference circuit (13c) ltc2323-16 with different external reference voltages figure?13. reference connections lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
18 232316 f16 frequency (mhz) amplitude (dbfs) 0 2.5 2 1 0.5 1.5 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 snr = 81.4db thd = ?86.8db sinad = 80.3db sfdr = 88.2db applications information periods, as shown in figure?14 , i refbuf quickly goes from approximately ~ 75a to a maximum of 500a for refout = 5v at 5msps . this step in dc current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at refout will affect the accuracy of the output code. due to the one-cycle conversion latency, the first conversion result at the beginning of a burst sampling period will be invalid. if an external reference is used to overdrive refout1,2 the fast settling ltc6655 reference is recommended. dynamic performance fast fourier transform (fft) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the ltc2323-16 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is bandlimited to frequencies from above dc and below half the sampling frequency. figure?16 shows that the ltc2323 -16 achieves a typical sinad of 80db at a 5mhz sampling rate with a 2.2mhz input. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure?16 shows that the ltc2323-16 achieves a typical snr of 81db at a 5mhz sampling rate with a 2.2mhz input. cnv 232316 f14 idle period figure?14. cnv waveform showing burst sampling figure?15. transient response of the ltc2323-16 figure?16. 32k point fft of the ltc2323-16 232316 f15 time (ns) output code (ch1, ch2) 0 200 100 35000 30000 25000 20000 15000 10000 5000 0 ?5000 ch2 ch1 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
19 applications information total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics. power considerations the ltc2323 -16 requires two power supplies: the 5v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2323 -16 to communicate with any digital logic operating between 1.8v and 2.5v . when using lvds i/o, the ov dd supply must be set to 2.5v. power supply sequencing the ltc2323 -16 does not have any specific power sup - ply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2323- 16 has a power-on-reset (por) circuit that will reset the ltc2323 -16 at initial power-up or whenever the power supply voltage drops below 2v. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 10ms after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. figure?17. power supply current of the ltc2323-16 versus sampling rate sample frequency (msps) 8 10 supply current (ma) 12 14 16 232316 f17 0 21 3 4 5 6 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
20 applications information timing and control cnv timing a rising edge on cnv initiates the acquisition phase and puts the internal sample-and-hold into the sample mode. a falling edge on cnv puts the internal sample-and-hold into the hold mode and starts a conversion cycle. the cnv pulse must be at least 25ns wide for proper opera - tion. cnv must be driven by a fast low jitter signal with a fall time from ov dd to below 100mv of less than 1ns. to achieve this fast falling edge, the distance from the cnv source to the cnv pin should be minimized. the trace for this pulse should be kept as narrow as possible and routed away from adjacent traces or planes to minimize capacitance. the drive strength of the gate driving the cnv line must be sufficient to yield a fast falling edge at the adc pin to below 100mv . we recommend the applica - tions circuit on page 26, which uses a high speed flip-flop to generate the cnv pulse to the adc, eliminating the effect of jitter from the fpga. if jitter from the fpga is not a concern, the flip-flop can be eliminated and replaced with an inverter such as the nc7sz04p5x sck serial data clock input the falling edge of this clock shifts the conversion result msb first onto the sdo pins. a 105mhz external clock must be applied at the sck pin to achieve 5msps throughput. clkout serial data clock output the clkout output provides a skew-matched clock to latch the sdo output at the receiver. the timing skew of the clkout and sdo outputs are matched. for high throughput applications, using clkout instead of sck to capture the sdo output eases timing requirements at the receiver. for low throughput speed applications, clkout + can be disabled by tying clkout C to ov dd . nap/sleep modes nap mode is a method to save power without sacrificing power-up delays for subsequent conversions. sleep mode has substantial power savings, but a power-up delay is incurred to allow the reference and power systems to become valid. to enter nap mode on the ltc2323-16, the sck signal must be held high or low and a series of two cnv pulses must be applied. this is the case for both cmos and lvds modes. the second rising edge of cnv initiates the nap state. the nap state will persist until either a single rising edge of sck is applied, or further cnv pulses are applied. the sck rising edge will put the ltc2323-16 back into the operational (full-power) state. when in nap mode, two additional pulses will put the ltc2323 -16 in sleep mode. when configured for cmos i/o operation, a single rising edge of sck can return the ltc2323-16 into operational mode. a 10ms delay is nec - essary after exiting sleep mode to allow the reference buf - fer to recharge the external filter capacitor. in lvds mode, exit sleep mode by supplying a fifth cnv pulse. the fifth pulse will return the ltc2323 -16 to operational mode, and further sck pulses will keep the part from re-entering nap and sleep modes. the fifth sck pulse also works in cmos mode as a method to exit sleep. in the absence of sck pulses, repetitive cnv pulses will cycle the ltc2323- 16 between operational, nap and sleep modes indefinitely. refer to the timing diagrams in figure?18, figure?19, figure?20 and figure?21 for more detailed timing information about sleep and nap modes. full power mode 1 2 cnv sck hold static high or low nap mode sdo1 sdo2 wake on 1st sck edge z z 232316 f18 figure?18. cmos and lvds mode nap and wake using sck lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
21 applications information full power mode 1 2 3 4 4.096v 4.096v refout recovery refout1 refout2 cnv sck hold static high or low nap mode sleep mode sdo1 sdo2 wake on 1st sck edge z z z z 232316 f19 t wake figure?19. cmos mode sleep and wake using sck 1 2 3 4 5 4.096v 4.096v refout recovery refout1 refout2 cnv sck hold static high or low nap mode sleep mode full power mode sdo1 sdo2 wake on 5th csb edge z z z z z 232316 f20 t wake b15 b14 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b13 t conv t acq serial data bits b[15:0] correspond to previous conversion cnv sck clkout sdo1,2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t cnvh hi-z hi-z t cyc 232316 f21 t dscklcnvh t dcnvsdoz t sck t sckl t sckh t dcnvsckl t dcnvsdov t dsclkclkout t dclkoutsdov t hsdo figure?20. lvds and cmos mode sleep and wake using cnv figure?21. ltc2323-16 timing diagram lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
22 applications information figure?22. ltc2323 using the lvds interface digital interface the ltc2323 -16 features a serial digital interface that is simple and straight forward to use. the flexible ov dd supply allows the ltc2323-16 to communicate with any digital logic operating between 1.8v and 2.5v. a 105mhz external clock must be applied at the sck pin to achieve 5msps throughput. in addition to a standard cmos spi interface, the ltc2323 - 16 provides an optional lvds spi interface to support low noise digital design. the cmos/lvds pin is used to select the digital inter face mode. the falling edge of sck outputs the conversion result msb first on the sdo pins. clkout provides a skew-matched clock to latch the sdo output at the receiver. the timing skew of the clkout and sdo outputs are matched. for high throughput applications, using clkout instead of sck to capture the sdo output eases timing requirements at the receiver. in cmos mode, use the sdo1 + , sdo2 + and clkout + pins as outputs. use the sck + pin as an input. do not connect the sdo1 C , sdo2 C , sck C and clkout C pins, as they each have internal pull-down circuitry to ognd. in lvds mode, use the sdo1 + /sdo1 C , sdo2 + /sdo2 C and clkout + /clkout C pins as differential outputs. these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). the sck + /sck C pins are differential inputs and must be terminated differentially by an external 100 resistor at the receiver (adc). 2.5v 2.5v ov dd ltc2323-16 fpga or dsp 232316 f22 sdo2 + sdo2 ? sck + sck ? clkout + clkout ? sdo1 + sdo1 ? cnv cmos /lvds + ? 100 + ? 100 + ? 100 + ? 100 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
23 figure?26. layer 4, bottom layer applications information figure?23. layer 1, top layer figure?24. layer 2, ground plane figure?25. layer 3, power plane board layout to obtain the best performance from the ltc2323-16, a printed circuit board is recommended. layout for the printed circuit board (pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals adjacent to analog signals or underneath the adc. recommended layout the following is an example of a recommended pcb lay - out. a single solid ground plane is used. bypass capaci - tors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise opera - tion of the adc. the analog input traces are screened by ground. for more details and information, refer to the dc1996, the evaluation kit for the ltc2323-16. lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
24 package description please refer to http://www.linear.com/product/ltc2323-16#packaging for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wghd-3). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0816 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev c) lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
25 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 05/14 changed y-axis units to dbfs updated sck, clkout sdo function descriptions changed snr penalty to 2db from 6db 6 8, 20, 22 14 b 4/17 changed cnv pin description and applications information changed fairchild components on typical application 8, 20 26 c 10/17 corrected minimum cnv pulse width to 25ns. 20 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16
26 ? linear technology corporation 2014 lt 1017 rev c ? printed in usa www.linear.com/ltc2323-16 related parts typical application part number description comments adcs ltc1407a/ltc1407a-1 12-/14-bit, 3msps simultaneous sampling adc 3v supply, 2-channel differential, 1.5msps per channel throughput, unipolar/bipolar inputs, 14mw, msop package ltc2314-14 14-bit, 4.5msps serial adc 3v/5v supply, 18mw/31mw, 20ppm/c max internal reference, unipolar inputs, 8-lead tsot-23 package LTC2321-16/ltc2321-14/ ltc2321-12 16-/14-/12-bit, 2msps, simultaneous sampling adcs 3.3v/5v supply, 33mw/ch, 10ppmc max internal reference, flexible inputs, 4mm 5mm qfn-28 package lt c2370-16/ltc2368-16/ ltc2367-16/ltc2364-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply , pseudo-differential unipolar input, 94db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply , differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages dacs ltc2632 dual 12-/10-/8-bit, spi v out dacs with internal reference 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 8-pin thinsot? package ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit spi v out dacs with external reference 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, 8-lead msop package references ltc6655 precision low drift, low noise buffered reference 5v/4.096v/3.3v/3v/2.5v/2.048v/1.25v, 5ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift, low noise buffered reference 5v/4.096v/3.3v/3v/2.5v/2.048v/1.25v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt1818/ lt1819 400mhz, 2500v/s, 9ma single/dual operational amplifiers C85dbc distortion at 5mhz, 6nv/hz input noise voltage, 9ma supply current, unity-gain stable lt1806 325mhz, single, rail-to-rail input and output, low distortion, low noise precision op amps C80dbc distortion at 5mhz, 3.5nv/hz input noise voltage, 9ma supply current, unity-gain stable lt6200 165mhz , rail-to-rail input and output, 0.95nv/ hz low noise, op amp family low noise, low distortion, unity-gain stable low jitter clock timing with rf sine generator using clock squaring/level-shifting circuit and retiming flip-flop nc7sz04p5x ( 3) 50 nc7sz04p5x conv enable master_clock conv 1k 1k ltc2323-16 232316 ta02 sdo1 sck gnd clr nl17sz74usg control logic (fpga, cpld, dsp, etc.) pre clkout cnv cmos /lvds v cc v cc q d sdo2 0.1f 10 10 10 lt c2323-16 232316fc for more information www.linear.com/ltc2323-16

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